Reset vector
The reset vector is the default location a central processing unit will go to find the first instruction it will execute after a reset. The reset vector is a pointer or address, where the CPU should always begin as soon as it is able to execute instructions. The address is in a section of non-volatile memory initialized to contain instructions to start the operation of the CPU, as the first step in the process of booting the system containing the CPU.
- The reset vector for the 8086 processor is at physical address FFFF0h (16 bytes below 1 MB). The value of the CS register at reset is FFFFh and the value of the IP register at reset is 0000h to form the segmented address FFFFh:0000h, which maps to physical address FFFF0h.
- The reset vector for the 80286 processor is at physical address 00FFFF0h (16 bytes below 1 MB). The value of the CS register at reset is F000h and the value of the IP register at reset is FFF0h to form the segmented address F000h:FFF0h, which maps to physical address 00FFFF0h in real mode.[1] This was changed to allow sufficient space to switch to protected mode without modifying the CS register.[2]
- The reset vector for the 80386 and later x86 processors is physical address FFFFFFF0h (16 bytes below 4 GB). The value of the selector portion of the CS register at reset is F000h, the value of the base portion of the CS register is FFFF0000h, and the value of the IP register at reset is FFF0h[3] to form the segmented address FFFFF000h:FFF0h, which maps to the physical address FFFFFFF0h in real mode.[4][5]
- The reset vector for PowerPC/Power Architecture processors is at an effective address of 0x00000100 for 32-bit processors and 0x0000000000000100 for 64-bit processors.
- The reset vector for SPARC version 8 processors is at an address of 0x00;[6] the reset vector for SPARC version 9 processors is at an address of 0x20 for power-on reset, 0x40 for watchdog reset, 0x60 for externally initiated reset, and 0x80 for software-initiated reset.[7]
References
- ↑ "iAPX 286 Programmer's Reference Manual" (PDF). Intel. 1983. Section 5.3 SYSTEM INITIALIZATION, p. 5-7. Retrieved November 3, 2013.
Since the CS register contains F000 (thus specifying a code segment starting at physical address F0000) and the instruction pointer contains FFF0, the processor will execute its first instruction at physical address FFFF0H.
- ↑ "iAPX 286 Programmer's Reference Manual" (PDF). Intel. 1983. Appendix D, iAPX 86/88 Software Compatibility Considerations, p. D-2. Retrieved November 3, 2013.
After reset, CS:IP = F000:FFF0 on the iAPX 286. This change was made to allow sufficient code space to enter protected mode without· reloading CS.
- ↑ "80386 Programmer's Reference Manual" (PDF). Intel. 1990. Section 10.1 Processor State After Reset, pages 10-1 - 10.3.
- ↑ "80386 Programmer's Reference Manual" (PDF). Intel. 1990. Section 10.2.3 First Instruction, p. 10-4. Retrieved November 3, 2013.
Execution begins with the instruction addressed by the initial contents of the CS and IP registers. To allow the initialization software to be placed in a ROM at the top of the address space, the high 12 bits of addresses issued for the code segment are set, until the first instruction which loads the CS register, such as a far jump or call. As a result, instruction fetching begins from address 0FFFFFFF0H.
- ↑ "Intel® 64 and IA-32 Architectures Software Developer's Manual" (PDF). Intel. May 2012. Section 9.1.4 First Instruction Executed, p. 2611. Retrieved August 23, 2012.
The first instruction that is fetched and executed following a hardware reset is located at physical address FFFFFFF0h. This address is 16 bytes below the processor’s uppermost physical address. The EPROM containing the software-initialization code must be located at this address.
- ↑ The SPARC Architecture Manual, Version 8 (PDF). SPARC International. p. 75.
- ↑ The SPARC Architecture Manual, Version 9 (PDF). SPARC International. pp. 109–112.
See also
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